Exemplary embodiments relate to a method of forming the metal lines of a semiconductor device and, more particularly, to a method of forming the metal lines of a semiconductor device, which is capable of improving a phenomenon in which a void is generated in the metal lines.
A semiconductor device includes conductive patterns stacked in multiple layers. The conductive patterns of the same layer may be formed within trenches, contact holes, or recess regions formed in an insulating layer and electrically isolated from each other. Furthermore, the conductive patterns of different layers may be electrically isolated from each other by an insulating layer or electrically coupled to each other through contact plugs. In a case where the conductive patterns of the semiconductor device are formed by using a damascene scheme, a driving failure may occur in the semiconductor device because of a void.
Hereinafter, the occurrence of a void in a process of forming the conductive patterns of a semiconductor device is described in detail with reference to FIG. 1. FIG. 1 shows an example of a process of forming the metal lines of a NAND flash memory device.
Referring to FIG. 1, in the NAND flash memory device including a plurality of cell strings, a plurality of insulating layers 5a, 5b may be stacked over the drain regions (not shown) of a cell string. Each of the drain regions is coupled to drain contact plugs 7 penetrating the insulating layers 5a, 5b formed over the drain regions. The drain contact plugs 7 may be formed by forming drain contact holes by removing the insulating layers 5a, 5b using an etch process to expose the drain regions, and then filling the drain contact holes with a conductive material.
Next, an etch stop layer 9 and an insulating layer 11 are formed over the insulating layer 5b including the drain contact plugs 7. Next, a plurality of trenches 15 are formed by removing the insulating layer 11 and the etch stop layer 9 formed over the drain contact plugs 7 to expose the drain contact plugs 7. Each of the trenches 15 is formed to expose a corresponding drain contact plug 7. However, with an increase of the degree of integration of semiconductor devices, a gap between the drain contact plugs 7 is narrowed, and so overlay margin between the drain contact plug 7 and a corresponding trench 15 becomes insufficient. If the drain contact plugs 7 and the trenches 15 are not properly arranged because of the shortage of overlay margin between the drain contact plugs 7 and the trenches 15, a problem may arise because neighboring drain contact plugs 7 are exposed through one trench 15. In this case, if bit lines are formed within the trenches 15 in a subsequent process, neighboring bit lines may be interconnected by the drain contact plug 7, resulting in a bridge between the bit lines. In order to prevent such a bridge, the trenches 15 are formed to have a reduced critical dimension (CD).
Next, in order to form metal lines, such as the bit lines, within the trenches 15, the trenches 15 are filled with a conductive material 17. However, since the critical dimension (CD) of the trenches 15 has been reduced in order to secure overlay margin, the aspect ratio of the trenches 15 has been increased. If the conductive material 17 is deposited to fill the trenches 15 in the state in which the aspect ratio of the trenches 15 has been increased as described above, the conductive material 17 is deposited thicker at the entrance of the trench 15 than on the sidewalk towards bottom of the trench 15. It leads to an overhang structure in which the width of the opened region at the entrance of the trench 15 is narrower than the width of the opened region towards the bottom of the trench 15. Consequently, before the trench 15 is fully filled with the conductive material 17, the entrance of the trench 15 is blocked by the conductive material 17, and so a void 19 may be formed within the trench 15. In this case, the bit lines may be disconnected, resulting in an operation failure of the semiconductor device. In particular, in a case where copper (Cu) is used as the conductive material 17 and deposited by using an electroplating method in order to improve resistance of the bit lines, barrier metal for preventing the diffusion of copper (Cu) and a seed layer for plating copper (Cu) is formed by using a chemical vapor deposition (CVD) method before forming a copper (Cu) layer. If the conductive material 17 is deposited by using a chemical vapor deposition (CVD) method as described above, an overhang structure is likely to occur. This makes it more difficult to fill the trenches 15 with the conductive material 17.